1. Field of the Invention
The present invention relates to the technical field of micro optoelectromechanical devices (MOEMS devices) and particularly, the present invention relates to the technical partial field of spatial light modulators on a semiconductor wafer.
2. Description of the Related Art
Spatial light modulators, also referred to as SLM, which are based on micromirrors for optical lithographic applications, require an exceptionally high mirror planarity to provide a tool having a high lithographic resolution and a dimensional or scalar uniformity. The conventional and currently used SLM technology based on aluminum mirrors has certain limitations or constraints in this regard. This technology is based on producing micromirrors on the top face of CMOS control electronics (CMOS=complementary metal oxide semiconductor) by using techniques for surface microprocessing (see also “Application of Spatial Light Modulator for Microlithography” by U. Dauderstädt, P. Dürr, T. Karlin, H. Schenk, H. Lakner, Proceedings of SPIE, vol. 5348, pp. 119-126, 2004). The reasons for limited planarity are:                a) The sacrificial layer comprises a polymer, which is also used to planarize the CMOS wafer and which works as spacer between the mirrors and the actuation electrodes. The planarization or leveling is achieved by chemical mechanical polishing (CMP) of the polymer, which removes residual surface roughness and levels out height differences on the wafer surface. The local planarity, which can be achieved is limited to a few nanometers. The mirror material is then sputtered directly onto the polymer sacrificial layer and any non-planarity in the spacer is directly transferred to the mirrors.        b) The mirror material is an aluminum alloy, having a grain structure with a grain structure in the range of several tens up to hundreds of nanometers. The grain structure is determined by the sputter conditions, such as sputter rate, pressure or temperature, as well as by the physical properties of the material on which sputtering is performed. Although it is possible to obtain a fairly homogeneous thin film with minor stress gradients, the alloy is subject to re-crystallization and stress relaxation upon heating and also sensitive to mismatch in contrast to the surrounding material, such as the spacer, during thermal expansion. The morphology of an aluminum alloy thin film can easily change as a result of changing processing conditions. Small changes in the crystal structure lead to stress gradients in the thin film that easily warps of deforms a micromirror made out of such an alloy. Thereby, it is extremely difficult to obtain a good mirror planarity. The statistical nature of the material itself as well as changes in the process conditions inevitably lead to a limited reproducibility and also, to a certain amount, to a dependency on a statistical spread of the planarity, so that it is impossible to perform an exact control and reproducibility of the planarity. For every large-area matrix-shaped spatial light modulator, a good matrix uniformity is of vital importance. Otherwise, the wafer-to-wafer and run-to-run reproducibility is limited. Further, an aluminum alloy is susceptible to plastic deformation upon bending. In that way, the mirror planarity can change during use, which limits the life span of such an SLM.        
A first approach for solving one of the above-mentioned problems could be the usage of monocrystalline silicon. Monocrystalline silicon is completely insensitive to processing temperature and has a coefficient of thermal expansion that is well matched to the rest of a CMOS wafer. It is possible to form micromirrors out of this material with a mirror planarity which is merely limited by the polishing quality of silicon, which is possible up to the range of atomic layers by using current techniques. Monocrystalline silicon is perfectly elastic and thus insensitive to plastic deformation upon use. Thus, the life time of the SLMs is not limited by material properties.
The idea of using monocrystalline silicon for producing spatial light modulators is not new. In the prior art, “flip chip” bonding of a structured micromirror on a wafer is disclosed, which comprises control electronics (see, for example, U.S. Pat. No. 6,587,613 B1, U.S. Pat. No. 6,800,210 B2 or U.S. Pat. No. 6,798,561 B2). These methods are based on separate fabrication of mirror structure (MEMS=micro-electromechanical systems) and control electronics (in CMOS technology). Then, the MEMS and CMOS are integrated by using an unspecified bonding method to join the two structures, which can either be performed on chip or wafer level. Another proposed method is based on a layer transfer of a monocrystalline thin film from a donor wafer, also referred to as SOI (SOI=silicon on insulator), onto a wafer containing control electronics, which can either be performed by eutectic bonding (for example according to WO 03/068669 A1) or by adhesive bonding (see, for example “Arrays of Monocrystalline Silicon Micromirrors Fabricated Using CMOS Compatible Transfer Bonding”, F. Niklaus, S. Haasl and E. Stemme, Journal of Micro-electromechanical Systems, vol. 12, no. 4, August 2003, pp. 465-469). A particular requirement for conventional spatial light modulators is the thickness of the mirrors, which should be in the range of 300 nanometers or less. However, up to now, such thin silicon membranes has not been successfully bonded to CMOS wafer, and thus the prior art has clear limits.
Further, the following disadvantages are to be mentioned concerning the prior art:
With regard to “flip chip” bonding of structured micromirrors (U.S. Pat. No. 6,587,613 B1, U.S. Pat. No. 6,800,210 B2 or U.S. Pat. No. 6,798,561 B2) it has to be said that this bonding requires a highly accurate alignment of the mirror structure with regard to the control electronics and that further the conditions for alignment accuracy increase rapidly with reduction of the pixel size, thus the method has limited scalability.
With regard to the layer transfer of monocrystalline silicon by eutectic bonding (WO 03/068669 A1) it has to be mentioned that this bonding of the wafers is based on forming an eutectic gold silicon alloy, which requires temperatures in excess of 363° Celsius and thus means a risk for increased stress in the transferred film. A further disadvantage is that an indiffusion of gold has to be performed, which can affect the mechanical performance of nearby elements, such as mirror hinges. Additionally, locally limited stress can be built up and crystal defects can occur at the bonded areas, which are sources for crack formation during thinning down. This is particularly a problem when very thin films, such as are required for spatial light modulators, have to be bonded. While this method of eutectic bonding has the advantage of being able to produce electrical and mechanical connections between mirrors and electronics directly without further processing (i.e. no filling elements are used), there is a disadvantage in that the area where bonding is performed is limited and in direct conflict to the requirement for compact post structures. A high mirror fill factor, which, on the one hand, requires small posts or plugs, respectively, and, on the other hand, a maximum bond area for ensuring a sufficient membrane integrity, requires thus two bonds which are mutually exclusive. Further, it has to be mentioned about eutectic bonding that it requires that a contact between post and film is achieved on all locations on the film, which is, however, very difficult, since                a) there are slight variations of the post heights, and        b) the mating wafers (i.e. the SOI wafer and the wafer providing the control electronics) have variations in thickness.        
Thereby, the difficulty is the strength of the wafers and the structures on the wafers, whereby bonding becomes sensitive to local height variations.
In relation to a layer transfer of a monocrystalline silicon by adhesive bonding (according to the above-mentioned disclosure of F. Niklaus, S. Haasl and G. Stemme) it has to be mentioned that this adhesive bonding has a limited bonding strength, caused by the dependence of the adhesive capability of the used adhesive material. Thus, the adhesive capability is highly dependent on the used material and thus at the same for all structures on the wafer. Additionally, it has to be mentioned that a thickness of a coating polymer is highly sensitive to a heavily structured surface topology. As long as no specific precautions are taken, the gap between the bonded wafers will be non-uniform and structure-dependent. Differences in the gaps between the mirrors and electrodes lead to variations in deflection properties.
Further, it is a disadvantage of adhesive bonding that outgassing can occur during bonding, which leads to the formation of bubbles. This problem of outgassing can be mitigated by bonding under vacuum, which requires a significant overhead by processing under vacuum. Further, it has to be mentioned that there is a risk of particle contamination prior to bonding caused by the lack of suitable bonding tools allowing cleaning immediately prior to bonding as a partial step of the bonding process. Further, it is a disadvantage of adhesive bonding that temperature limitations occur due to material instability, such as material flow or decomposition at elevated temperatures, which might exclude the usage of W-CVD (W-CVD=tungsten based chemical vapor deposition) for forming the planar surface after bonding. Further, it has to be mentioned that non-ideal material properties, such as sodium contamination of certain polymers cause incompatibility with CMOS electronics or with standard microfabrication processes.
Further, WO 03/025986 A1 discloses a bonding method, where the contact posts are formed between the mirror membrane and electrodes after bonding. This patent application discloses, in a general way, method steps required for a successful fabrication of actual SLM devices. However, the fabrication method described herein can be further improved in several aspects, since merely a general list of different generally possible methods is disclosed and only little specific information about the processing conditions is mentioned. For example, the claims include all possible ways of bonding substrates. In this patent application, particularly basic processing conditions for bonding with an adhesive material, such as a photoresist, are disclosed (page 9 of WO 03/025986 A1). Further, the above-mentioned patent application remains non-specific about how a thin film is to be deposited on the electronic substrate. Additionally, no direct information is given on how this is to be performed particularly with a monocrystalline silicon thin film. The disclosure in the above-mentioned patent application that thinning down of part of the silicon wafer can be performed (such as disclosed on page 3 and 7 of the mentioned patent application), would cause problems when the goal is a 300 nm thick membrane, since the accuracy of such a process is very poor. Further, in the above-mentioned patent application, it is described very generally how the connection of the electrical/mechanical connections between the silicon membrane and the electronics can be made. Additionally, in the above-mentioned patent application, it is only discussed very generally that the bonding material has to be removed in order to make the micromirrors moveable. However, it is not discussed anywhere how this could be performed.